May 2015 edition – Vol.7 no.5

Financial support of our strategic cluster
The management team of ReSMiQ was expecting the decision of the Fonds de recherche du Québec – Nature et technologies (FRQNT) pertaining to the grant renewal application for our strategic cluster. The FRQNT recently inform us about the decision to renew ReSMiQ for the next 6 years with an annual contribution of $432,000.00. During the renewal process the ReSMiQ received the highest score for each evaluation criteria and the highest amount granted by the FRQNT in the 2015-2016 contest. The center’s management would like to thank everyone who has contributed in the growth of ReSMiQ and provided a significant effort in the production of this application. More details

Microfluidic day at Université Laval (May 27)
The ReSMiQ is proud to support local initiatives for training and dissemination of knowledge activities. The latest is the microfluidics half day held at Université Laval on May 27 and co-organized by Dr. Miled, in order to promote research in microfluidics. This event was also sponsored by CMC Microsystems and Quebec Section of the IEEE. The program included a poster presentation session, invited talks offered by professors Miled, Greener, Larachi and Taghavi, a presentation by B. Mallard CMC, a keynote talk offered by David Juncker from McGill, and finally a panel session on the theme of the establishment of a first workshop on microfluidics in Quebec. More details
microfluidic_ULavalFrom left to right: Paul Fortier, Président IEEE-Québec, Amine Miled Co-président du réseau de recherche en microfluidique à l’université Laval et du chapitre IEEE-EMBS/CAS Québec, David Juncker, Conférencier invité de l’Univ. McGill, Jesse Greener, Co-président du réseau de recherche en microfluidique à l’université Laval, Robert Mallard, CMC Microsystèmes.

2015 ReSMiQ’s annual symposium (May 29)
We held our annual symposium during the 83rd Sawan from Polytechnique Montréal and professor Bahoura from Université du Québec à Rimouski. It was a real pleasure and with great enthousiasm that we welcomed our guest speakers, including professor Wei Shi of the Université Laval and professor Bahoura, and all 30 participants who attended this edition. On this occasion, members of ReSMiQ presented their research and exchanged views on several issues related to microsystems. Seventeen students participated in the scientific posters competition, and the judges were impressed by the high quality of the work presented. Furthermore, 3 of them have received awards for their excellent presentations. We take this opportunity to invite you to be part of our next annual symposium within the next conference of ACFAS to be held in Montréal at UQAM on May 2016. Detailed program

ReSMiQ intensive course
Pr. Carlos Galup Montoro from the l’Universidade Federal de Santa Catarina in Brazil presented the intensive course entitled “Ultra-Low-Voltage (ULV) IC Design” at Polytechnique Montréal, organized as part of our continuing training program in collaboration with the IEEE Montréal’s chapters of the Solid State Circuit Society (SSCS) and the Circuits and Systems Society (CASS).
See the abstract


– Dr. Sawan from Polytechnique Montréal offered two keynote speeches at the 6th MCETECH conference on e-technologies (Montréal) and the CIIA’2015 conference (Algeria). Details for MCETECH / Details for CIIA’2015

– Dr. Fréchette from Université de Sherbrooke is supervising Andréane D’Arcy-Lepage and Mahmood R. S. Shirazi who respectively won the second place of the undergraduate student expo and the audience choice award at the ASME-IMECE, held in Montréal.

– Dr. Miled from Université Laval is supervising Adnane Kara who won the ReSMiQ-CMC award of the best scientific poster at the 1st Microfluidic Day held at Université Laval in Québec City.

– Dr. Sawan from polytechnique Montréal received the Shanghai Municipality International Collaboration Award. More details

– Dr. Gosselin and Dr. Shi from Université Laval, Dr. Sawan and Dr. Savaria from Polytechnique Montréal, and 4 other colleagues received financing from the innovation fund of the Canada Foundation for Innovation for the development of shared research infrastructures at Université Laval.

– Dr. Izquierdo, Dr. Deslandes, Dr. Nabki and Dr. Boukadoum from Université de Québec à Montréal, received financing from the innovation fund of the Canada Foundation for Innovation for the project “Plateforme pour la conception, la caractérisation et l’intégration de dispositifs nanoscopiques dans des microsystèmes”.

– Dr. Massicotte from Université du Québec à Trois-Rivières received an ENGAGE grant from NSERC with

– Dr. Gosselin and Dr. Miled from Université Laval were awarded the prize for best new chapter 2015 from the IEEE Engineering in Medicine & Biology Society for the IEEE CAS/EMB Quebec Chapter.



Scholarships and awards
– Microsystems Experimental Demonstration Competition

Undergraduate and graduate students are invited to demonstrate their scientific and technical expertise during the 4th edition of the ReSMiQ Innovation Day by submitting their project. More than 5 000$ in awards.
More details

SIGNAL is the main monthly information medium of the Microsystems Strategic Alliance of Québec (ReSMiQ). This newsletter aims to be an active link between the members of ReSMiQ and all individuals who have an interest in research and innovation in microsystems. We commit ourselves to promote in it our members’ research and increase ReSMiQ’s visibility.

ReSMiQ is a group of researchers in an interuniversity research center that can count on the support of the Fonds de recherche du Québec – Nature et technologies (FRQNT) and ten (10) Quebec universities involved in microsystems research.

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Call for contributions

12th NAMIS international Autumn school,
from september 10 to 14, 2018, Seattle, USA.

Submission deadline : May 18, 2018.
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Conference on Design and Architectures for Signal and Image Processing (DASIP),
du 9 au 12 octobre 2018, Porto, Portugal.
Submission deadline : May 25, 2018.
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IEEE Biomedical Circuits and Systems Conference (BioCAS2018),
from October 17 to 19, 2018, Cleveland, U.S.A.
Submission deadline : June 11, 2018.
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IEEE Life Science Conference (LSC2018),
from October 28 to 30, 2018, Montréal, Canada

Submission deadline : June 4, 2018.
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Call for participation

31st Canadian Conference on Electrical & Computer engineering (CCECE),
from May 13 to 16, 2018, Québec, Canada.
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2018 International Symposium on Circuits and Systems (ISCAS),
from May 27 to 30, 2018, Florence, Italy.

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16th IEEE International NEWCAS Conference (NEWCAS),
from June 24 to 27, 2018, Montréal, Canada.
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The 31st International Conference on Industrial, Engineering & Other Applications of Applied Intelligent Systems (IAE-AIE2018),
from June 25 to 28, 2018, Montréal, Canada.
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18th International Forum on MPSoC for Software-defined Hardware (MPSoC’18),
from July 29 to August 3, 2018, Snowbird, UT, USA.

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61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS),
from August 5 to 8, 2018, Windsor, ON, Canada.
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12th International Conference on Verification and Evaluation of Computer and Communication Systems (VECoS 2018),
du 26 au 28 septembre 2018, Grenoble, France.

Plus de détails

XXXIII  Conference on design of circuits and integrated systems (DCIS),
from November 14 to 16, 2018, Lyon, France.
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Prof. Claude Thibeault
École de technologie supérieure
Member of ReSMiQ since 1992

Claude ThibeaultProf. Claude Thibeault received his Ph.D. in Electrical Engineering from Ecole Polytechnique de Montreal, Canada. Currently, he is with the Electrical Engineering Department of Ecole de technologie superieure, Montreal, Canada, where he serves as full professor. He has successfully conducted several research projects supported by the industry to develop prototypes and products for wireless communication, digital video, and radar detection, among others. His research interests include design and verification methodologies targeting ASICs and FPGAs, radiation effects, defect and fault tolerance approaches, as well as current-based IC test and diagnosis. He holds 13 patents and has published more than 130 journal and conference refereed papers, which have been cited more than 730 times. He has co-authored papers that have been awarded as the best in their category at international conferences. Prof. Thibeault has been a member of different conference committees, including the IEEE VLSI Test Symposium, for which he was program chair in 2010-2012, and general chair in 2014-2015. More information

Below is a selection of publications in recent years followed by representative work.

Ghodbane, A, Saad, M., Boland, J.F. Et Thibeault, C., “Applied actuator fault accommodation in flight control systems using fault reconstruction based FDD and SMC reconfiguration “, International Journal of Computer, Information, Systems and Control Engineering, vol. 8, no. 7. p.1044-1049, 2014.

Hoque, K. A., Mohamed, O.A., Savaria, Y., Thibeault, C., “Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking”, Formal Techniques for Safety-Critical Systems, Springer, 2014.

Tazi F.Z., Thibeault, C., Savaria, Y., Pichette, S., Audet, Y., “On Extra Delays Affecting I/O blocks of an SRAM FPGA Due to Ionizing Radiations”, IEEE Trans. on Nuclear Science, Vol. 61, No. 6, pp.3138-3145, 2014

Darvishi, M., Audet, Y., Blaquière, Y., Thibeault, C., Pichette, S., Tazi F.Z., “Circuit Level Modeling of Extra Combinational Delays in SRAM-Based FPGAs Due to Transient Ionizing Radiation”, IEEE Trans. On Nuclear Science, vol. 61, no 6, p. 3535-3542, 2014

Sarkis, G., Giard, P., Thibeault, C., Gross, W., “Fast Polar Decoders: Algorithm and Implementation”, IEEE JOURNAL on Selected Areas in Comm.,vol 32, no 5, p. 946-957, 2014.

Hobeika, C., Pichette, S., Ghodbane, A., Thibeault, C., Audet, Y., Saad, M., Boland, J.F., “Flight Control Fault Models Based on SEU Emulation”, SAE Int. J. Aerosp. 6(2):643-649, 2013.

Thibeault, C., Hariri, Y., Hasan, S.R., Hobeika, C., Savaria, Y., Audet, Y., Tazi F.Z., “A Library-Based Early Soft Error Rate Estimation Technique for SRAM-based FPGA Design”, Journal of Electronic Testing: Theory and Applications, Springer, vol. 29, no. 4, p. 457-471, 2013


Fast Polar Decoders: Algorithm and Implementation

Polar codes are the first error-correcting codes with an explicit construction to provably achieve the symmetric capacity of memoryless channels. They have two properties that are of interest to data storage systems: a very low error-floor due to their large stopping distance, and low-complexity implementations. However, polar codes have two drawbacks: their performance at short to moderate lengths is inferior to that of other codes, such as low-density parity-check (LDPC) codes; and their low-complexity decoding algorithm, successive-cancellation (SC), is serial in nature, leading to low decoding throughput. In this work, we focus on improving the throughput of polar decoders. By building on the ideas used for SSC and ML-SSC decoding, namely decoding constituent codes without recursion, and recognizing further classes of constituent codes that can be directly decoded, we present a polar decoder that, for a (32768, 29492) code, is 40 times faster than the best SC decoder when implemented on the same field-programmable gate-array (FPGA). For a (16384, 14746) code, our decoder is more than 8 times faster than the state of the art polar decoder in litterature, again when implemented on the same FPGA. Additionally, the proposed decoder is flexible and can decode any polar code of a given length.

The overall architecture of our decoder is shown in Fig. 1. At the beginning, the instructions (program) are loaded into the instruction RAM (instruction memory) and fetched by the controller (instruction decoder). The controller then signals the channel loader to load channel LLRs into memory, and data processing unit (ALU) to perform the correct function. The processing unit accesses data in Formula and Formula-RAMs (data memory). The estimated codeword is buffered into the codeword RAM which is accessible from outside the decoder. By using a pre-compiled list of instructions, the controller is reduced to fetching and decoding instructions, tracking which stage is currently decoded, initiating channel LLR loading, and triggering the processing unit. In Tables I, II and III are shown comparisons of simulations results from this work and the state-of-the-art works reported in literature using SP-SC, TPSC, and LDPC codes, respectively.

Fig. 1. The top-level architecture of the decoder.

Table I. Information Throughput Comparison for Codes of Length 32768 on the Altera Stratix IV EP4SGX530KH40C2.

Table II. Post-Fitting and Information Throughput Results for a (16384, 14746) Code on the Altera Stratix IV EP4SGX530KH40C2.

Table III. Comparison with an LDPC Code of Similar Error Correcting Performance, on the XILINX Virtex VI XC6VLX550TL.