March 2018 edition – Vol.10 no.3


The ReSMiQ management team is preparing the 2017 annual report, which will be ready for the annual general meeting of the members, as well as for the annual meeting of the Board of Directors of the Center to be held during the month of May 2018. These activities will allow us to take stock of the past year and focus on future directions. So to disseminate our results and encourage our student researchers, ReSMiQ organizes its annual symposium to be held on May 18th.

To meet the expectations of the FRQNT, we compile the major infrastructures and laboratories under the direction of the members of ReSMiQ to enrich the annual report and the website of the Center. Our members are invited to give us the name of their laboratory by April 5th. As for the annual symposium, the program will be posted online in the next few days and students have until April 9th ​​to submit their proposals for contributions to the poster competition. We serve our members and promote the conditions for student researchers to go the extra mile to innovate.

We are also pleased to announce that ReSMiQ has a new member, professor Sharmistha Bhadra of the Electrical and Computer Engineering Department at McGill University. Her research interests lie in the areas of printed and flexible hybrid electronics, micro/nanoelectronics, and RF/microwave circuits and systems.

ReSMiQ is a group of researchers in an interuniversity research center that can count on the support of the Fonds de recherche du Québec – Nature et technologies (FRQNT) and nine (9) Quebec universities involved in microsystems research.



– Dr. Zhu from Concordia U. received a collaborative research and development grant (CRD) from NSERC entitled Deep Neural Network-based Speech Enhancement for Robust Speech Recognition in Smart Home Device in partnership with the company Microsemi Semiconductors in Ottawa.


Upcoming Seminar

Speaker: David Stoppa, AMS, Switzerland
 Time of Flight 3D Sensing and Imaging: detectors, readout circuits and data processing
Polytechnique Montréal, Pavillon Lassonde, L-2712 
10:00 am tp 12:00 noon

Abstract and biography

Scientific poster competition
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A New Wearable Brain Scanner: A helmet records wearers’ brain activity using magnetoencephalography (MEG) while they move around. More details

Organ-on-Chips get smart and go electric: Human Organs-on-Chips technology has been enhanced to non-invasively report cells’ health, electrical activities and differentiation status. More details

To Speed Up AI, Mix Memory and Processing: New computing architectures aim to extend artificial intelligence from the cloud to smartphones. More details

Low-cost wearables manufactured by hybrid 3D printing: New method combines precision printing of stretchable conductive inks with pick-and-place of electronic components to make flexible, wearable sensors. More details

Carbon Nanomaterials Could Push Copper Aside in Chip Interconnects: The days of copper interconnects are numbered and carbon nanomaterials are poised to take up the job. More details

Intel’s 49-Qubit Chip Shoots for Quantum Supremacy: Intel’s new superconducting quantum chip called Tangle Lake has enough qubits to make things very interesting from a scientific standpoint. The company has passed a key milestone while running alongside Google and IBM in the marathon to build quantum computing systems. More eétails

SIGNAL is the main monthly information medium of the Microsystems Strategic Alliance of Québec (ReSMiQ). This newsletter aims to be an active link between the members of ReSMiQ and all individuals who have an interest in research and innovation in microsystems. We commit ourselves to promote in it our members’ research and increase ReSMiQ’s visibility.

ReSMiQ is a group of researchers in an interuniversity research center that can count on the support of the Fonds de recherche du Québec – Nature et technologies (FRQNT) and nine (9) Quebec universities involved in microsystems research.

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Call for participation

32nd IEEE Canadian Conference on Electrical and Computer Engineering (CCECE),
from May 5 to 8, 2019, Edmonton, Canada.

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2019 International Symposium on Circuits and Systems (ISCAS),
from May 26 to 29, 2019, Sapporo, Japan.

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17th IEEE International NEWCAS Conference (NEWCAS),
from June 23 to 26, 2019, Munich, Germany.
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The 32nd International Conference on Industrial, Engineering & Other Applications of Applied Intelligent Systems (IAE-AIE)
from July 9 to 11, 2019, Graz, Austria.

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62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS),
from August 4 to 7, 2019, Dallas, United States.

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Call for contributions

XXXIV Conference on design of circuits and integrated systems (DCIS),
from November 20 to 22, 2019, Bilbao, Spain.

Submission deadline: April 30, 2019.
More details

The Conference on Design and Architectures for Signal and Image Processing (DASIP)
from October 16 to 18, 2019, Montréal, Canada.

Submission deadline: May 17, 2019.
More details

IEEE Biomedical Circuits and Systems Conference (BioCAS2019),
from October 17 to 19, 2019, Nara, Japan.

Submission deadline: June 10, 2019.
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Prof. Brett Meyer
McGill University

Member of ReSMiQ since 2013

Brett Meyer received his Ph.D. degree in Electrical Engineering and Computer Engineering from Carnegie Mellon University, Pittsburgh, USA. He is currently an Associate Professor in the Department of Electrical and Computer Engineering at McGill University, Montreal, QC, Canada. His research interests include the design and architecture of resilient multiprocessor computer systems, the algorithms for automatically designing and optimization machine learning hardware and software, and the cybersecurity for automotive and aerospace systems. Prof. Meyer’s research has been recognized with Best Paper awards and nominations in several conferences. He has also served on the Technical Program Committees of many international conferences. He has filed one patent and published more than 40 papers in peer review journals and conferences proceedings. More details

Below is a selection of publications in recent years followed by representative work.

  1. J. Caplan, Z. Al-bayati, H. Zeng, B. H. Meyer. (2018). Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy. IEEE Transactions on Computers (IEEE TC). 67(4): 582-588.
  2. M. I. Mera, J. Caplan, S. H. Mozafari, B. H. Meyer, and P. Milder. (2017). Area, throughput, and power trade-offs for FPGA- and ASIC-based execution stream compression. ACM Trans. Embed. Comput. Syst.(TECS). 16(4): 1-20.
  3. C. Ma, A. Mahajan, and B. H. Meyer. (2017). “Multi-armed bandits for efficient lifetime estimation in MPSoC design,” Design, Automation Test in Europe Conference Exhibition (DATE), Mar. 2017, pp. 1–6.
  4. S. H. Mozafari and B. H. Meyer. (2016). Efficient performance evaluation of multi-core SIMT processors with hot redundancy. IEEE Transactions on Emerging Topics in Computing (TETC). DOI: 10.1109/TETC.2016.2594957.
  5. R. Zhang, B. H. Meyer, K. Wang, M. R. Stan, and K. Skadron. (2016). Tolerating the consequences of multiple EM-induced C4 bump failures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI). 24(6): 2335-2344.
  6. S. C. Smithson, G. Yang, W. J. Gross, and B. H. Meyer. (2016). “Neural networks designing neural networks: Multi-objective hyper-parameter optimization,” Computer-Aided Design (ICCAD), 2016 IEEE/ACM International Conference on, Nov., pp. 1–8.


Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy

Embedded systems in several domains such as avionics and automotive are subject to inspection from certification authorities. These authorities are interested in verifying the safety-critical aspects of a system and, typically, do not certify non-critical parts. The design of such Mixed-Criticality Systems (MCS) has received increasing attention in recent years. However, although MCS must be designed to overcome transient faults, their susceptibility to transient faults is often overlooked. In this paper, we consider the problem of mapping and scheduling efficient, certifiable MCS that can survive transient faults. We generalize previous MCS models and analysis to support On-Demand Redundancy (ODR). A task set transformation is proposed to generate a modified task set that supports various forms of ODR while satisfying reliability and certification requirements. The analysis is incorporated into a design space exploration algorithm that supports a wide range of fault-tolerance mechanisms and heterogeneous platforms. Experiments show that ODR can improve Quality of Service (QoS) provided to non-critical tasks by 29 percent on average, compared to lockstep execution. Moreover, combining several fault-tolerance mechanisms can lead to additional improvements in schedulability and QoS.

Fig. 1. The four-mode system model. The modes are denoted LO (low), TF (transient faults), OV (task overruns), and HI (high).

Fig. 2. ODR (On-demand redundancy) provides better QoS in multicore systems as utilization increases. The QoS for MIX and ODR is on average 20 percent better than for LS and 30 percent in the worst case. (LS: two pairs of lockstep cores, MIX: one lockstep pair and one ODR pair, ODR: two ODR pairs with only DMR).