March 2016 edition – Vol.8 no.3


The month of march is keeping us very busy in order to finalize the scientific program and the social activities for ISCAS2016. The preparation for our annual report are underway in order to deliver it in time during the month of May. We have announced the call for contribution for the next edition of the ReSMiQ annual symposium to be held on May 22nd at the Sheraton Hotel. In 2016 we are joining forces with colleagues from France and Japan and doing so giving our annual symposium international scope. We’ll have guest speakers who will talk about the impact of circuits and systems on human health and quality of life. A poster competition featuring projects by graduate will also be part of the program. The call for communications has been broadcasted a few days ago. Interested students must send us their proposal  no later than April 12, 2016 using the poster proposal form available via the ReSMiQ web site. More details

We are also focusing on the organization of the next edition of the ReSMiQ Innovation Day (RID). Following the success of the RID2015 (see Signal Vol.7 no.9) we are preparing the next edition which will be held on October 13th. Participants will attend the keynote speeches, discussion panel and numerous presentations by representatives from academia and industry. A special session is dedicated to the presentation of undergraduate and graduate student projects where they will demonstrate their scientific and technical expertise during a competition where each presenter will display their project via a technical demonstration, a live experiment. Prizes will be awarded to the best presentations. Visit to see all the details. We remind you that this competition is open to all full-time students enrolled in a university or a college/CEGEP in the province of Québec. The Call for projects has been announced and students interested in submitting their project can do so until May 9, 2016. We are counting on all members to encourage their students to participate. More details


– Dr. Sawan from Polytechnique Montréal offered a seminar at KAUST in Saudi Arabia. More details

– Dr. Nicolescu from Polytechnique Montréal, Dr. Trajkovic from Concordia and Dr. Liboiron-Ladouceur from McGill are co-authors of a paper that won the best poster award at ACP2016, and another paper that won the best paper award at DATE2016.

– Sawan from Polytechnique Montréal was appaointed ambassador of Montréal for his contribution with the Palais des congrès of the city. More details



This month’s seminar

Seminar_TCarusone_a_smallPr. Tony Chan Carusone from the University of Toronto presented the intensive course entitled “CMOS Transceiver Circuits for Short-Reach Optical Communication” at Polytechnique Montréal, organized as part of our continuing training program in collaboration with the IEEE Montréal’s chapters of the Solid State Circuit Society (SSCS) and the Circuits and Systems Society (CASS). See the abstract. Abstract & biography

Upcoming seminar
ReSMiQ and the Chapter of the IEEE Solid-State Circuits Society (SSCS) in collaboration with the IEEE Circuits and Systems Society (CASS) invite you to attend the following seminar to be held on April 22, 2016, at 9:00 am at Polytechnique Montréal.

Speaker: Seong Hwan Cho, Korea Advanced Institute of Science and Technology (KAIST)
Sensor electronics and Time-domain analog signal processing
Abstract and biography

SIGNAL is the main monthly information medium of the Microsystems Strategic Alliance of Québec (ReSMiQ). This newsletter aims to be an active link between the members of ReSMiQ and all individuals who have an interest in research and innovation in microsystems. We commit ourselves to promote in it our members’ research and increase ReSMiQ’s visibility.

ReSMiQ is a group of researchers in an interuniversity research center that can count on the support of the Fonds de recherche du Québec – Nature et technologies (FRQNT) and ten (10) Quebec universities involved in microsystems research.

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Call for participation

32nd IEEE Canadian Conference on Electrical and Computer Engineering (CCECE),
from May 5 to 8, 2019, Edmonton, Canada.

More details

2019 International Symposium on Circuits and Systems (ISCAS),
from May 26 to 29, 2019, Sapporo, Japan.

More details

17th IEEE International NEWCAS Conference (NEWCAS),
from June 23 to 26, 2019, Munich, Germany.
More details

The 32nd International Conference on Industrial, Engineering & Other Applications of Applied Intelligent Systems (IAE-AIE)
from July 9 to 11, 2019, Graz, Austria.

More details

62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS),
from August 4 to 7, 2019, Dallas, United States.

More details

Call for contributions

XXXIV Conference on design of circuits and integrated systems (DCIS),
from November 20 to 22, 2019, Bilbao, Spain.

Submission deadline: April 30, 2019.
More details

The Conference on Design and Architectures for Signal and Image Processing (DASIP)
from October 16 to 18, 2019, Montréal, Canada.

Submission deadline: May 17, 2019.
More details

IEEE Biomedical Circuits and Systems Conference (BioCAS2019),
from October 17 to 19, 2019, Nara, Japan.

Submission deadline: June 10, 2019.
More details


Prof. W. J. Gross
McGill University
Member of ReSMiQ since 2005

wjg_small2Warren J. Gross received the Ph.D. in Electrical Engineering from the University of Toronto, Ontario, Canada. Currently, he is a Professor and the Director of the Integrated Systems for Information Processing Laboratory in the Department of Electrical and Computer Engineering, McGill University, Montréal, Québec, Canada. He has held positions as an engineer in Netpec Design Group Ltd and as Chief Architect and President/CEO in WideSail Technologies Inc. His research interests are in the design and implementation of signal processing systems and custom computer architectures. He holds 6 patents, has published 3 book chapters and many papers in refereed journals and international conferences. Dr. Gross served as Chair of the IEEE Signal Processing Society Technical Committee, as Technical Program Co-Chair of the IEEE Workshop on Signal Processing Systems (SiPS 2012) and as Chair of the IEEE ICC 2012 Workshop on Emerging Data Storage Technologies. Dr. Gross has also served as Associate Editor for the IEEE Transactions on Signal Processing. He is a Senior Member of the IEEE and a licensed Professional Engineer in the Province of Ontario. More details

Below is a selection of publications in recent years followed by representative work.

  1. Hemati, F. *Leduc-Primeau, and W. J. Gross, “A Relaxed Min-Sum LDPC Decoder with Simplified Check Nodes,” IEEE Communications Letters, vol. 20, no. 3, pp. 422-425, March 2016.
  2. *Sarkis, P. *Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Fast List Decoders for Polar Codes,” IEEE Journal on Selected Areas in Communications, vol. 34, no. 2, pp. 318-328, February 2016.
  3. *Onizawa, H. *Jarollahi, T. Hanyu, and W. J. Gross, “Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on Multiple-Valued Logic and Applications, vol. 6, no. 1, pp. 13-24, March 2016.
  4. *Leduc-Primeau, V. *Gripon, M. Rabbat, and W. J. Gross, “Fault-Tolerant Associative Memories Based on c-Partite Graphs,” IEEE Transactions on Signal Processing, vol. 64, no. 4, pp. 829-841, February 15 2016.
  5. *El-Kurdi, D. *Fernández, W. J. Gross, and D. Giannacopoulos, “Acceleration of the Finite Element Gaussian Belief Propagation Solver Using Minimum Residual Techniques,” IEEE Transactions on Magnetics, vol. 52, no. 3, pp. 1-4, March 2016.
  6. Onizawa, D. Katagiri, K. Matsumiya, W. J. Gross, and T. Hanyu, “Gabor Filter Based on Stochastic Computation,” IEEE Signal Processing Letters, vol. 22, no. 9, pp. 1224-1228, September 2015.
  7. *Jarollahi, V. *Gripon, N. *Onizawa, and W. J. Gross, “Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 4, pp. 642-653, April 2015.
  8. P. *Giard, G. *Sarkis, C. Thibeault, and W. J. Gross, “237 Gbit/s Unrolled Hardware Polar Decoder,” Electronics Letters, vol. 51, no. 10, pp. 762-763, May 14 2015.


Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks

This paper presents algorithms and hardware implementations (Fig.1) of associative memories based on multiple-valued sparse clustered networks (MV-SCNs). SCNs are recently-introduced binary-weighted associative memories that significantly improve the storage and retrieval capabilities over the prior state-of-the art. However, deleting or updating the messages stored in binary-weighted connections result in a significant increase in the data retrieval error probability as the binary-weighted connections deleted may be shared for several data patterns. In order to address the problem, the proposed algorithm exploits multiple-valued weighted connections of the network for storing the messages while maintaining the number of computation nodes in a cluster. The use of the multiple-valued weighted connections reduces the probability of deleting the shared connections compared to the binary-weighted connections. As a result, the proposed algorithm lowers the message error rate (MER) by an order of magnitude for our sample network with 60% deleted contents compared to the conventional algorithm when the same amount of memory is used (Fig 2). For performance comparisons in hardware, the proposed SCNs are designed using Verilog-HDL and synthesized on TSMC 65 nm CMOS technology. The synthesis results show that the proposed MV-SCNs are around 10% smaller than the conventional binary-weighted SCNs as the number of computation nodes in the proposed SCNs is smaller than that of the conventional SCNs with the comparable speed and memory size.


Fig. 1. Overall structure of an MV-SCN for different architectures (I,II, and III) where c clusters are designed. Only a global decoder is different at each architecture.


Fig. 2. Effect of increasing the deletion rate on the MER in architecture II for binary- and multiple-valued weighted SCNs in case of storing the same amount of messages: (a) M=92 (d=0.3) and (b) M=131 (d=0.4). M: number of messages; d: density. The MER achieved from the Architecture II, with 60% deleted contents and loaded with 40% density (d=0.4) (b), is 12.8-fold smaller than that of the conventional work with a similar amount of memory usage.