January 2018 edition – Vol.10 no.1


We have taken steps to organize the next annual symposium to be held in Montreal on May 18, 2018. The program will feature the most recent work of keynote speakers and graduate students will present their own work during the poster competition. The best presentations will be rewarded with a cash prize. Visit the web page (resmiq.org > Students > Scientific poster competition) for more details. Also, we remind you that the deadline for papers submission is February 17, 2018. The executive committee strongly encourages all the members of ReSMiQ to submit their contributions and to participate in large numbers. Paper submission

ReSMiQ is a group of researchers in an interuniversity research center that can count on the support of the Fonds de recherche du Québec – Nature et technologies (FRQNT) and nine (9) Quebec universities involved in microsystems research.


– Dr. Boukadoum from Université du Québec à Montréal offered a tutorial entitled « Artificial neural networks for biomedical analysis and circuit synthesis » at the IEEE Life Sciences Conference (LSC 2017) held  from December 13 to 15, 2017 in Sydney, Australia.
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– Dr. Beltrame from Polytechnique Montréal is visiting professor at the Wilhelm-Schickhard Institute for Computer Science at the University of Tübingen until August 2018.

– Dr. Savaria and Dr. David from Polytechnique Montréal are supervising Michel Gémieux at the Ph.D. who is the recipient of an Hydro-Québec scholarship.

– Dr. Massicotte from UQTR received two (2) grants from MITACS as part of their Accelerate program in partnership with the company Opal-RT.

– Dr. Massicotte from UQTR is one of the committee members of the research tools and instruments grants program (RTI) of the NSERC for 2017-2018.


Jerald Yoo, a Solid State Circuits Society (SSCS) Distibguished Lecturer (DL), from the National University of Singapore, offered a seminar entitles «Design strategies for wearable sensor interface circuits – from electrodes to signal processing» at Polytechnique Montréal as part of ReSMiQ’s training activities in partnership with the Montréal chapter of the IEEE-SSCS.

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Scientific poster competition

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Scholarships and financial support

Financial support for invited researcher
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Financial support for undergraduate students
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Financial support for conference participants
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SIGNAL is the main monthly information medium of the Microsystems Strategic Alliance of Québec (ReSMiQ). This newsletter aims to be an active link between the members of ReSMiQ and all individuals who have an interest in research and innovation in microsystems. We commit ourselves to promote in it our members’ research and increase ReSMiQ’s visibility.

ReSMiQ is a group of researchers in an interuniversity research center that can count on the support of the Fonds de recherche du Québec – Nature et technologies (FRQNT) and nine (9) Quebec universities involved in microsystems research.

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Call for contributions

12th NAMIS international Autumn school,
from september 10 to 14, 2018, Seattle, USA.

Submission deadline : May 18, 2018.
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Conference on Design and Architectures for Signal and Image Processing (DASIP),
du 9 au 12 octobre 2018, Porto, Portugal.
Submission deadline : May 25, 2018.
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IEEE Biomedical Circuits and Systems Conference (BioCAS2018),
from October 17 to 19, 2018, Cleveland, U.S.A.
Submission deadline : June 11, 2018.
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IEEE Life Science Conference (LSC2018),
from October 28 to 30, 2018, Montréal, Canada

Submission deadline : June 4, 2018.
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Call for participation

31st Canadian Conference on Electrical & Computer engineering (CCECE),
from May 13 to 16, 2018, Québec, Canada.
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2018 International Symposium on Circuits and Systems (ISCAS),
from May 27 to 30, 2018, Florence, Italy.

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16th IEEE International NEWCAS Conference (NEWCAS),
from June 24 to 27, 2018, Montréal, Canada.
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The 31st International Conference on Industrial, Engineering & Other Applications of Applied Intelligent Systems (IAE-AIE2018),
from June 25 to 28, 2018, Montréal, Canada.
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18th International Forum on MPSoC for Software-defined Hardware (MPSoC’18),
from July 29 to August 3, 2018, Snowbird, UT, USA.

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61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS),
from August 5 to 8, 2018, Windsor, ON, Canada.
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12th International Conference on Verification and Evaluation of Computer and Communication Systems (VECoS 2018),
du 26 au 28 septembre 2018, Grenoble, France.

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XXXIII  Conference on design of circuits and integrated systems (DCIS),
from November 14 to 16, 2018, Lyon, France.
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Prof. Jean-Pierre David
Polytechnique Montréal
Member of ReSMiQ since 2003

Jean Pierre David received a Ph.D. in Applied Sciences from the Catholic University of Louvain, Belgium. He worked as a researcher at the Laboratory of Integrated Devices and Electronic Circuits (DICE) at the Catholic University of Louvain. He was an adjunct professor at the University of Montreal, in the Laboratory of Analysis and Synthesis of Ordinary Systems (LASSO). Currently, he is Associate Professor in the Department of Electrical Engineering and a member of the Research Group in Microelectronics and Microsystems (GR2M) at École Polytechnique in Montreal, Canada. His current research interests are mainly in the design, configuration and programming of digital systems; programmable logic systems (e.g., FPGAs, processors, microcontrollers) and their applications, particularly in real-time simulations (Hardware In the Loop - HIL), telecommunications (e.g., network monitoring, 5G), and neural networks. Professor David is the author or co-author of more than 65 articles in peer-reviewed international conferences and journals and holds two patents. He is a member of IEEE and ReSMiQ.

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Below is a selection of publications in recent years followed by representative work.

  1. Montano, F., Ould-Bachir, T. & David, J.P. (2017). An Evaluation of a High-Level Synthesis Approach to the FPGA-based Sub-microsecond Real-Time Simulation of Power Converters. IEEE Transactions on Industrial Electronics. 65(1), 636-644.
  2. David, J.P. (2016). Low latency and division free Gauss-Jordan solver in floating point arithmetic. Journal of Parallel and Distributed Computing, 106, 185-193.
  3. Larbanet, A., Lerebours, J. & David, J.P. (2015). Detecting very large sets of referenced files at 40/100 GbE, especially MP4 files. Digital Investigation, 14(suppl. 1), S85-S94.
  4. Courbariaux, M., Bengio, Y., & David J.P. (2015) Binaryconnect: Training deep neural networks with binary weights during propagations - Advances in Neural Information Processing Systems, 2015 (+ 270 citations).
  5. Daigneault, M.-A. & David, J.P. (2014). Fast description and synthesis of control-dominant circuits. Computers and Electrical Engineering, 40(4), 1199-1214.
  6. Bachir, T.O., Dufour, C., Belanger, J., Mahseredjian, J. & David, J.P. (2013). A Fully Automated Reconfigurable Calculation Engine Dedicated to the Real-Time Simulation of High Switching Frequency Power Electronic Circuits. Mathematics and Computers in Simulation, 91, 167-177.
  7. Ould-Bachir, T. & David, J.P. (2013). Self-alignment schemes for the implementation of addition-related floating-point operators. ACM Transactions on Reconfigurable Technology and Systems, 6(1).


Binaryconnect: Training deep neural networks
with binary weights during propagations

Deep  Neural  Networks  (DNN)  have  achieved  state-of-the-art  results  in  a  wide range of tasks,  with the best results obtained with large training sets and large models.  In the past, GPUs enabled these breakthroughs because of their greater computational speed.  In the future, faster computation at both training and test time is likely to be crucial for further progress and for consumer applications on low-power devices.  As a result, there is much interest in research and development of dedicated hardware for Deep Learning (DL). Binary weights, i.e., weights which are constrained to only two possible values (e.g. -1 or 1), would bring great benefits to specialized DL hardware by replacing many multiply-accumulate operations by simple accumulations, as multipliers are the most space and power-hungry  components  of  the  digital  implementation  of  neural  networks.   We  introduce BinaryConnect, a method which consists in training a DNN with binary weights during the forward and backward propagations, while retaining precision of  the  stored  weights  in  which  gradients  are  accumulated.   Like  other  dropout schemes,  we  show  that  BinaryConnect  acts  as  regularizer  and  we  obtain  near state-of-the-art results with BinaryConnect on the permutation-invariant MNIST, CIFAR-10 and SVHN.

The impact of such a method on specialized hardware implementations of deep networks could be major, by removing the need for about 2/3 of the multiplications, and thus potentially allowing to speed-up by a factor of 3 at training time.

Test error rates of DNNs trained on the MNIST (no convolution and no unsupervised pretraining), CIFAR-10 (no data augmentation) and SVHN, depending on the method are shown below. We see that in spite of using only a single bit per weight during propagation, performance is not worse than ordinary (no regularizer) DNNs, it is actually better, especially with the stochastic version, suggesting that BinaryConnect acts as a regularizer.