April 2015 edition – Vol.7 no.4

2014 annual report and general assembly of members
Our latest annual report is now available (2014 annual report). Also, we remind all members of ReSMiQ that our next general assembly will be held on May 7, 2015 at Polytechnique Montréal. We will present the annual report of our activities and elect the members of the executive committee as well as the board of directors for 2015-2016. The attending members will vote on the Director’s election for the next term.

Financial support of our strategic cluster
The management team of ReSMiQ is expecting the decision of the Fonds de recherche du Québec – Nature et technologies (FRQNT) pertaining to the grant renewal application for our strategic cluster which should be announced very soon. After sending the letter of intent in May 2014 and a full application in October, we met with the visiting committee last January. The center’s management would like to thank everyone who contributed in the growth of ReSMiQ and provided a considerable effort in the production of this application. Also, we take the opportunity of the results of the latest NSERC discovery grant program to congratulate all our members who have just renewed their grant this year and particularly all applicants who saw a significant increase.

The 13th edition of NEWCAS will be held in Grenoble on June 7 to 10. The call for papers has generated a record number of 326 articles submissions. We encourage all our members to participate in the next edition. ReSMiQ will, as for every edition, provide a valuable financial assistance.

4th edition of the ReSMiQ Innovation day (RID2015)
The 4th edition of the ReSMiQ Innovation Day (RID) will be held on October 15, 2015. This competition is open to all full-time students enrolled in a university or a college/CEGEP in the province of Québec. The call for project has been sent out and all students interested in showing their research can submit it until May 4, 2015. We are counting on all members to encourage their students to participate and circulate this announcement among their colleagues in connected fields.
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The organization of the 2016 edition of the IEEE International Symposium on Circuits and Systems Conference has started this month with the first formal meeting of the local organizing committee with representatives of IEEE Meetings, Conferences & Events (MCE ), Tourism Montreal and representatives of the Sheraton Montreal. A special delegation will be present at the 2015 edition in Lisbon month of May to promote MOntréal and ISCAS2016. Thus, the technical committee will take the opportunity to meet and establish the conference program.

ReSMiQ Seminar
C_BajRossiCamilla Baj-Rossi from the École polytechnique fédérale de Lausanne in Switzerland presented a seminar entitled “Implantable Device for Monitoring Drugs and Metabolites in Small Animals for Applications in Personalized Medicine” at Polytechnique Montréal, organized as part of our continuing training program in collaboration with the IEEE Montréal’s chapter of the Solid State circuit society (SSCS) and the Circuits and Systems Society (CASS).
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– Dr. Savaria from Polytechnique Montréal is visiting the ENSEIRB-IMS Laboratory at Bordeaux, France, as invited researcher.

– Dr. Savaria from Polytechnique Montréal presented an invited seminar at UNISTRA of Strasbourg, France.

– Dr. Sawan from Polytechnique Montréal is chairing for two years the selection committee of the IEEE Biomedical Engineering Award.
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– Dr. Lakhssassi from Université du Québec en Outaouais received an ENGAGE grant from NSERC with the TRIFIDE Group.

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– Dr. Ahmad from Concordia received the IEEE Circuits and Systems Society 2015 award for chapter of the year in Region 1-7.
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Intensive course
ReSMiQ and the Chapters of the IEEE Solid-State Circuits Society (SSCS) in collaboration with the IEEE Circuits and Systems Society (CASS) invites you to attend the following seminar to be held on May 14, 2015, at 10:30 AM at Polytechnique Montréal.
Carlos Galup-Montoro , Universidade Federal de Santa Catarina (UFSC), Brazil

Title: Ultra-Low-Voltage (ULV) IC Design
Abstrac and biography

ReSMiQ annual symposium
Date: Mai 29, 2015
Place: Université du Québec à Rimouski (UQAR) Rimouski
Important: Transport and lodging for our members will be partially supported by ReSMiQ through a financial support of 200$.
Registration instructions and programme détaillé

Scholarships and awards
– Microsystems Experimental Demonstration Competition
Undergraduate and graduate students are invited to demonstrate their scientific and technical expertise during the 4th edition of the ReSMiQ Innovation Day by submitting their project. More than 5 000$ in awards.
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SIGNAL is the main monthly information medium of the Microsystems Strategic Alliance of Québec (ReSMiQ). This newsletter aims to be an active link between the members of ReSMiQ and all individuals who have an interest in research and innovation in microsystems. We commit ourselves to promote in it our members’ research and increase ReSMiQ’s visibility.

ReSMiQ is a group of researchers in an interuniversity research center that can count on the support of the Fonds de recherche du Québec – Nature et technologies (FRQNT) and ten (10) Quebec universities involved in microsystems research.

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Call for participation

32nd IEEE Canadian Conference on Electrical and Computer Engineering (CCECE),
from May 5 to 8, 2019, Edmonton, Canada.

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2019 International Symposium on Circuits and Systems (ISCAS),
from May 26 to 29, 2019, Sapporo, Japan.

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17th IEEE International NEWCAS Conference (NEWCAS),
from June 23 to 26, 2019, Munich, Germany.
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The 32nd International Conference on Industrial, Engineering & Other Applications of Applied Intelligent Systems (IAE-AIE)
from July 9 to 11, 2019, Graz, Austria.

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62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS),
from August 4 to 7, 2019, Dallas, United States.

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Call for contributions

XXXIV Conference on design of circuits and integrated systems (DCIS),
from November 20 to 22, 2019, Bilbao, Spain.

Submission deadline: April 30, 2019.
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The Conference on Design and Architectures for Signal and Image Processing (DASIP)
from October 16 to 18, 2019, Montréal, Canada.

Submission deadline: May 17, 2019.
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IEEE Biomedical Circuits and Systems Conference (BioCAS2019),
from October 17 to 19, 2019, Nara, Japan.

Submission deadline: June 10, 2019.
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Prof. Yvon Savaria
Polytechnique Montréal
Member of ReSMiQ since 1991

Yvon Savaria received the Ph.D. degree in Electrical Engineering from McGill University, Canada. Since 1985, he has been with the Polytechnique Montreal, where he is currently Professor. During several years, he was Chairman of the Department of Electrical Engineering. He has carried out work in several areas related to microelectronic circuits and microsystems. Currently, he is involved in several projects that relate to aircraft embedded systems, green IT, wireless sensor network, virtual network, computational efficiency and application specific architecture design. Professor Savaria holds 16 patents, has published more than 400 journal and conference refereed papers, and has been the thesis director of 140 graduate students. He was co-chairman at the International conferences on Application-specific Systems, Architecture and Processors (ASAP) in 2006 and 2007, respectively. He has been working as a consultant or was sponsored for carrying research by Bombardier, CNRC, Design Workshop, Dolphin, DREO, Genesis, Gennum, Hyperchip, ISR, LTRIM, Miranda, MiroTech, Nortel, Octasic, PMC-Sierra, Technocap, Thales, Tundra and VXP. He was a member and chairman of CMC Microsystems board. He was awarded a Tier-1 Canada Research Chair on design and architectures of advanced microelectronic systems. He received the Synergy Award of the Natural Sciences and Engineering Research Council of Canada (NSERC), and is Fellow of the Institute of Electrical and Electronics Engineers (IEEE). More information

Below is a selection of publications in recent years followed by representative work.

LAFLAMME-MAYER. N., BLAQUIERE, Y., SAVARIA, Y. and SAWAN, M. (2014) « A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems » IEEE Transaction on CAS 1, 66(11), pp. 3135-44.

KOWARZYK, G., BÉLANGER, N., HACCOUN, D., SAVARIA, Y. (2013) « Optimizing the Parallel Tree-Search for Finding Shortest-Span Error-Correcting CDO Codes », IEEE Transactions on Parallel and Distributed Systems, 25(1), pp. 2992-01.

FISCHER, A., PLAMONDON, R., SAVARIA, Y., RIESEN, K., and BUNKE, H. (2014). « A Hausdorff Heuristic for Efficient Computation of Graph Edit Distance ». In Structural, Syntactic, and Statistical Pattern Recognition Springer Berlin Heidelberg, pp. 83-92.

FARAH, R., GAN, Q., LANGLOIS, J. P., BILODEAU, G. A., and SAVARIA, Y. (2014). « A computationally efficient importance sampling tracking algorithm ». Machine Vision and Applications, pp. 1-17.

GAN, Q., LANGLOIS, J. P., and SAVARIA, Y. (2014). « A Parallel Systematic Resampling Algorithm or High-Speed Particle Filters in Embedded Systems ». Circuits, Systems, and Signal Processing, pp. 1-12.

GAN, Q., LANGLOIS, J. P., and SAVARIA, Y. (2014). « Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations ». Journal of Signal Processing Systems, 75(3), pp. 191-202.

SHAHEEN, M. A., SAVARIA, Y., and HAMOUI, A. A. (2014). « Design and Modeling of High-resolution Multibit Log-domain Delta Sigma Modulators ». Analog Integrated Circuits and Signal Processing, 79(3), pp. 569-582.

HOQUE, K. A., AIT-MOHAMED, O., SAVARIA, Y., & THIBEAULT, C. (2014). Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking. In Formal Techniques for Safety-Critical Systems, pp. 54-70.


A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems

A novel platform for rapidly prototyping, the WaferBoard, is being developed in our lab to accelerate the time to market of microelectronic systems of increasingly complexity. This platform is based on an active surface implemented using a 200 mm full wafer device. This active surface is covered with over 1.2 million tiny conductive pads called NanoPads interconnected with a configurable interconnection networks. Every Unit-Cell comprises a 4 × 4 array of NanoPads, and a 32×32 array of Unit-Cells defines a reticle image. The assembly at wafer-scale level is called WaferIC and is achieved by photo-repeating 76 copies of the reticle image that are stitched together to implement wafer scale interconnections (Fig. 1). We propose in this paper a novel configurable multi-power-rail pad that combines power supply support circuits and a digital input/output (I/O) buffers designed for a wafer-scale system. This wafer-scale platform includes a reconfigurable wafer-scale circuit, the WaferIC, comprising an alignment-insensitive surface that can be configured to interconnect any digital components manually deposited on its surface. The proposed multi-power-rail pad minimizes power losses and heat dissipation within the circuit. The pad that is fed from two distinct voltage sources providing power at 1.8 and 3.3 V has been implemented and tested. This pad has two merged configurable control loops that can select the power source. Merging takes place through shared transistors. This dual supply pad embeds a voltage regulator that achieves a fast response time of 21.1 ns and that can operate over a wide range of configurable regulated output voltage, from 500 mV up to 2.955V. This regulator is capable of providing a maximum output current of 40 mA while needing only a very small quiescent current of 126 μA. The regulator's power supply noise rejection ranges from -25 down to -40 dB for frequencies ranging from 1 kHz up to 1 MHz. The embedded digital I/O pad shares a common output with the power distribution and can be configured from 0.5 up to 3.3 V for a maximum speed of 250 MHz.
Fig. 1. (a) WaferIC with user integrated circuits (uICs) deposited on its alignment insensitive surface. (b) Platform cross-section where pressure in the thermal pouch ensures good electrical contact between uIC balls and the nanopads through a z-axis film. (c) Interconnection of uICs through the wafernet.